For many years, optical lenses and semiconductor wafers have been polished by chemical-mechanical means. More recently, this technique has been applied as a means of planarizing intermetal dielectric layers of silicon dioxide and for removing portions of conductive layers within integrated circuit devices as they are fabricated on various substrates. For example, a conformal layer of silicon dioxide may cover a metal interconnect such that the upper surface of the layer is characterized by a series of non-planar steps corresponding in height and width to the underlying metal interconnects.
The rapid advances in semiconductor technology has seen the advent of very large scale integration (VLSI) and ultra large scale integration (ULSI) circuits resulting in the packing of very many more devices in smaller areas on a semiconductor substrate. The greater device densities require greater degrees of planarity to permit the higher resolution lithographic processes required to form the greater number of devices having smaller features as incorporated in current designs. Moreover, copper, because of its low resistance, is increasingly being used as interconnects. Conventionally, etching techniques are used to planarize conductive (metal) and insulator surfaces. However, certain metals, desirable for their advantageous properties when used as interconnects (Au, Ag, Cu) are not readily amenable to etching, thus the need for chemical-mechanical polishing (CMP).
Typically, the various metal interconnects are formed through lithographic or damascene processes. The damascene technique is described in U.S. Pat. No. 4,789,648, to Chow, et al. assigned to the assignee of the present invention, the entire contents of which are incorporated herein by reference. For example, in a lithographic process, a first blanket metal layer is deposited on a first insulating layer, following which electrical lines are formed by subtractive etching through a first mask. A second insulating layer is placed over the first metallized layer, and holes are patterned into the second insulating layer using a second mask. Metal columns or plugs are formed by filling the holes with metal. A second blanket metal layer is formed over the second insulating layer, the plugs electrically connecting the first and second metal layers. The second metal layer is masked and etched to form a second set of electrical lines. This process is repeated as required to generate the desired device.
Presently, VLSI uses aluminum for the wiring and tungsten for the plugs because of their susceptibility to etching. However, the resistivity of copper is superior to either aluminum or tungsten, making its use desirable, but copper does not have desirable properties with respect to etching.
Variations in the heights of the upper surface of the intermetal dielectric layer have several undesirable characteristics. The optical resolution of subsequent photolithographic processing steps may be degraded by non-planar dielectric surfaces. Loss of optical resolution lowers the resolution at which lines may be printed. Moreover, where the step height is large, the coverage of a second metal layer over the dielectric layer may be incomplete, leading to open circuits.
In view of these problems, methods have been evolved to planarize the upper surfaces of the metal and dielectric layers. One such technique is chemical-mechanical polishing (CMP) using an abrasive polishing agent worked by a rotating polishing pad. A chemical-mechanical polishing method is described in U.S. Pat. No. 4,944,836, Beyer, et al., assigned to the assignee of the present invention, the entire contents of which are incorporated herein by reference. Conventional polishing pads are made of a relatively soft and flexible material, such as nonwoven fibers interconnected together by a relatively small amount of a polyurethane adhesive binder, or may be laminated layers with variations of physical properties throughout the thickness of the pad. Multilayer pads generally have a flexible top polishing layer backed by a layer of stiffer material.
The CMP art combines the chemical conversion of a surface layer to be removed, with the mechanical removal of the conversion product. Ideally, the conversion product is soft, facilitating high polishing rates. CMP pads must resolve two constraints relevant to the present invention. The surface in contact with the substrate to be polished must be resilient. Of particular relevance to the present invention is the problem of local over polishing, also known as “dishing”, resulting from too flexible a pad. This is one of the key problems encountered during CMP of metal substrates. Also, an increased number and density of defects in the polished surface may be caused by frayed and loose fibers that develop as conventional fibrous pads become worn. Such defects correlate with low yields of product.
Some of the most commonly used polishing pads for manufacturing semiconductor chips are a very soft foam pad, or a soft nonwoven fiber pad. An advantage of a soft polishing pad is low defect density on the polished wafer and good within-wafer uniformity. However, soft CMP pads suffer from very short pad life requiring replacement after polishing about 50 wafers, and excessive dishing of the polished wafer because of the pad softness. Also, for a metal damascene CMP process, a soft pad usually causes much more dishing compared with a hard pad.
It is generally known that prevention of dishing requires a stiffer pad. Thus, a hard polishing pad usually has better planarization capability than a soft pad. However, the defects count is much higher than with the soft pad and the within-wafer uniformity is usually much worse. In addition, hard pads may be conditionable, which means that the pad surface condition can be regenerated using a diamond disk or an abrasive roller to recondition the pad surface by removing worn areas and embedded debris. This reconditioning capability means that a hard pad may last much longer than a soft pad. Such reconditioning in situ also means that polishing tool down time for pad replacement is greatly reduced.
Currently, these problems are handled using multi-step techniques wherein initial polishing is effected at a high rate using one set of pads and abrasive compounds, followed by a second polishing step using a second set of pads and abrasive compounds differently optimized in comparison to the first set. This is a time consuming process and, moreover, it also suffers from high defect densities due to the use of two different pads. For Cu planarization, CMP pads are critical, and are as important as the abrasive slurry. Fibrous pads of the prior art have been too soft to obtain good planarization. Stacked nonwoven fiber and other types of pads have previously been tried in an attempt to obtain better CMP performance. However, thin (5 to 20 mils thick) pads of nonwoven fibers bound with polyurethane are not sufficiently durable and do not long survive the CMP process.
Accordingly, the need exists for improved fibrous polishing pads. A high quality CMP pad should meet the following requirements: produce extremely low defects counts on polished surfaces, cause extremely small dishing and extremely low erosion of polished surfaces, and have a long pad life extendible by reconditioning. None of the existing prior art CMP pads can meet all of these requirements, which are needed for the future generation of CMP processes. A new type of CMP pad is therefore needed to meet these requirements.